Threshold Switching Enabled Sub-pW-Leakage, Hysteresis-Free Circuits

In this article, we present ultralow leakage logic circuits by combining 3-D memristors with CMOS transistors. Significant current reductions of up to 99% are found experiments and simulation for a memristive hybrid-inverter if compared conventional inverter. Likewise, circuit simulations hybrid ring oscillators, NAND, or full adders show more than 100% gain in energy efficiency per cycle over state-of-the-art circuits. Importantly, the offer hysteresis-free operation. The operation is due properly engineered properties-such as threshold voltage-of match circuit, well self-adaptive filament diameter our memristor during Lastly, feature 10 8 ON- OFF ratio, enabling both high speed low (~10 fA) when integrated transistor. They also come well-controlled formation on ~10-nm footprint, making them ideal integrate modern technology